This invention relates to memory cells for use in a dynamic random access memory (DRAM) and, more particularly, to a memory cell that uses a dielectrically-filled vertical trench as a storage node and a vertical transistor as a switch located over the trench.
DRAMS have become among the most important of the integrated circuit devices and are the source of continuing research and development which, in particular, aims to increase their storage capacity and writing and reading speeds. This has necessitated the use of smaller and more closely spaced memory cells for use in the memory arrays. Of increasing significance are memory cells in which the storage node is provided by a polysilicon-filled trench in a silicon chip and the switching transistor is a vertical transistor located in the chip over the trench. It is known that a DRAM that uses a MOSFET as the switching transistor. The two output current terminals of the transistor alternate between source and drain roles as the storage node is charged and discharged. As such, each of these terminals can be described as a source/drain and a drain/source, as is appropriate for the particular role. For purposes of discussion, these terminals are simply referred to as a source/drain. The vertical transistor is located over the storage node in a manner which renders the surface area of the chip used by the cell to be essentially the same as that used by the vertical trench. Ideally, a cell using a vertical transistor can provide higher packing densities than a cell that uses a horizontal switching transistor that is positioned adjacent to the trench that provides the storage node. One type of a vertical transistor over a vertical trench cell is described in U.S. patent application Ser. No. 08/770,962, filed on Dec. 20, 1996, in which Norbert Arnold is the inventor and the assignee is the same as that of the present application.
A memory cell of the present invention has a unique structure fabricated by a novel process. In one embodiment, a semiconductor chip is first provided with a vertical trench to be used in forming the storage capacitor of the cell. After the trench is made, the dielectric of the capacitor is formed by coating its walls with a dielectric material. The storage node of the capacitor is provided by a doped polysilicon fill of the trench. The top portion of the trench is provided with essentially monocrystalline silicon, suitable for forming one source/drain of the vertical transistor. An additional silicon layer, intermediately placed between two dielectric layers, is subsequently deposited over the chip. The three layers are apertured in the region over the trench to expose the top of the fill. Typically, this layer is polysilicon. The walls of the additional polysilicon layer that were exposed in the aperturing operation are oxidized to form the gate dielectric of the transistor. The aperture is then filled with silicon that is appropriate to form the intermediate layer of the transistor in which there is to be created during operation the inversion layer that forms the channel between the source/drain regions of the transistor. Ultimately an additional silicon layer is formed that will form with this intermediate layer the second source/drain region of the transistor. A bit line connection is made to this last-mentioned layer, and a word line is provided by the apertured polysilicon layer.
Another embodiment of the present invention is directed to a memory cell that is for use in a memory array of rows and columns of memory cells within a monocrystalline bulk portion of a silicon chip and that is addressed by word lines and bit lines. The memory cell comprises a capacitor, a vertical transistor, a word line, and a bit line. The capacitor comprises a vertical trench filled with silicon and having a layer of dielectric along its wall that isolates the silicon fill from the bulk portion of the chip. The vertical transistor is superposed over the trench and has a first source/drain merged with the silicon at the top of the trench, an intermediate silicon layer that is merged with the silicon fill at the top of the trench to form the first source/drain region, and in which an inversion layer is to be created to form a conductive channel, a second source/drain region overlying the intermediate silicon layer, a gate dielectric layer surrounding the intermediate silicon layer, and a gate surrounding the gate dielectric layer and extending along the surface of the chip and dielectrically insulated therefrom and being coupled to a word line. The bit line is in electrical contact with the second source/drain and otherwise extends over the surface of the trench and is electrically insulated from the word line and from the chip.
In another embodiment, the invention is a novel process of fabricating the cell that includes imparting seed information to the polysilicon deposited in the trench. This seed information makes it possible to provide a semiconductor intermediate layer wherein the channel of the transistor can be created.
In another embodiment, the present invention is directed to a process for making a memory cell. The process comprises the steps of forming a trench in a semiconductor chip of one conductivity type; forming a dielectric layer over the walls of the trench; filling the trench with polysilicon of a conductivity type opposite that of the chip; growing an epitaxial silicon layer over the surface of the chip of sufficient thickness for forming over the top of the trench a layer of essentially monocrystalline silicon of a conductivity that is opposite that of the chip for serving as a first source/drain; forming a first dielectric layer over the surface of the chip; forming a polysilicon layer of the conductivity type opposite that of the chip over the surface of the first dielectric layer; forming a second dielectric layer over the surface of said polysilicon layer; etching an opening through the first and second dielectric layers and said polysilicon layer to bare the essentially monocrystalline silicon over the top of the trench; forming a silicon oxide layer selectively along the sidewall of the opening in the polysilicon layer; growing monocrystalline silicon of the one conductivity type in the opening for forming an intermediate layer in which there will be formed the channel of a vertical transistor in which the silicon oxide layer over the sidewall of said polysilicon layer of the opening serves as the gate dielectric; and depositing a conductive layer of the opposite conductivity type over the top surface of the chip that contacts the intermediate silicon layer for serving as a second source/drain and bit line of the cell.
The invention will be better understood from the following more detailed description taken in conjunction with the accompanying drawing.